The present invention relates generally to testing of integrated circuits and, more specifically, to a method for performing fast sequential access of circuit nodes and a circuit for use therewith.
As the density of circuit boards containing integrated circuits (ICs) increases, it becomes more difficult to access the board signal wires using metal probes, or a xe2x80x9cbed of nailsxe2x80x9d. This has led to the development by members of the Institute of Electrical and Electronic Engineers (IEEE) of two test standards for circuit board testing. The standard for accessing digital signals of integrated circuit (IC) pins is denoted 1149.1 and was first published in 1990. An extension to the 1149.1 standard that is aimed at accessing analog signals is denoted 1149.4 and was first published Mar. 28, 2000, though preliminary drafts of the standard were available to many people prior to that date.
The 1149.4 standard will be better understood by reference to FIG. 1 which illustrates general architecture of an IC 10 which contains 1149.4 test access circuitry. The 1149.4 standard extends the 1149.1 digital test access port (TAP) 12 by adding two analog test bus pins 14 and 16, denoted AT1 and AT2, to allow the signal at any function pin of an IC to be accessed via these two pins. To monitor the voltage at a function pin 18 via an analog test bus pin 16, two switches are enabled. As shown in FIG. 2, which illustrates an analog boundary module (ABM) 20, one switch 22 (or 24) for function pin 18, and one (not shown) in a test bus interface circuit (TBIC) 26 for the IC. Common signals generated by the TAP to control all ABMs may include ShiftDR 30, ClockDR 32, UpdateDR 34, and one or more Mode signals 36 and 38. To enable the two switches, appropriate logic bits are shifted serially, or xe2x80x9cscannedxe2x80x9d, through a boundary scan register (BSR) linked by wires following the path of dashed line 40, such that a scan register update latch 42 (or 44) controlling each switch is loaded with the logic bits. The boundary scan shift register has N bits, where N is any non-zero integer, and hence N or more clock cycles are required to shift in bits to all of the boundary scan shift register elements (or stages).
Each time a function pin signal is to be accessed, it is necessary to perform at least the sequence of steps described below (where xe2x80x9ctogglexe2x80x9d means xe2x80x9cgenerate a rising and falling edge onxe2x80x9d), according to the 1149.1/1149.4 TAP controller state diagram shown in FIG. 3 (and in the waveforms of FIG. 7). The numerals 1 or 0 adjacent the states are prescribed values of the TMS input to the TAP.
The sequence of steps are: 1. while TMS=1, toggle TCK to proceed from Run-test/Idle state 50, Update-DR state 52 or Update-IR state 54 to Select-DR-Scan state 56; 2. while TMS=0, toggle TCK to proceed from Select-DR-Scan state 56 to Capture-DR state 58, in which new data overwrites the BSR contents via multiplexer 60 (FIG. 2) and other multiplexers; 3. while TMS=0, toggle TCK to proceed from Capture-DR state 58 to Shift-DR state 62; 4. while TMS=0, repeatedly toggle TCK to scan in N bits to completely fill the BSR shift register elements 64, 66, 68 and 70, in FIG. 2; 5. while TMS=1, toggle TCK to proceed from Shift-DR state 62 to Exit1-DR state 72; and 6. while TMS=1, toggle TCK to proceed from Exit1-DR state 72 to Update-DR state 52, which updates all update latches 42, 44, 74 and 76, in FIG. 2 to output new bit values.
The minimum number of TCK clock cycles to select a different analog switch to be enabled is therefore NTCK=4+N. The number of boundary scan shift register bits per ABM, as required by 1149.4, is four (elements 64, 66, 68, 70, in FIG. 2). Four shift register bits are also required in the TBIC 26. Some of the pins of the IC may be digital, and hence may not have an associated ABMxe2x80x94these pins may have only one boundary scan bit per pin and still be compatible with 1149.4 and 1149.1. Although 1149.4 is intended to provide analog access to analog pins, it can also be used to provide analog access to digital pins as suggested by S. Sunter in xe2x80x9cCost/benefit analysis of the P1149.4 mixed-signal test busxe2x80x9d in IEE Proceedings, Circuits, Devices, and Systems, December 1996, on pages 394 and 395. This allows a tester to measure the DC characteristics of all pins of an IC via the TAP and analog bus pins, thus greatly reducing the number of probes needed to probe ICs on a wafer and the number of channels needed in a tester. To enable this simplification in test equipment, every pin must have an ABM. Therefore, for an IC with P pins, N=4P+4 bits would be needed. For P greater than 100, N is approximately equal to 4P.
Clock frequencies for TCK, when testing a stand-alone IC, typically range from fTCK=1 MHz to fTCK=50 MHz. The time to scan in N bits is NTCK/fTCK. If the time to measure each pin""s voltage is TMeasure, the total time per pin measurement is TMeasure+NTCK/fTCK. The time to measure the voltage at P pins is therefore:
P(TMeasure+NTCK/fTCK)=P(TMeasure+4P/fTCK)=PTMeasure+4P2/fTCK) 
which is proportional to the square of the number of pins.
To measure the standard DC characteristics of a pin, six voltages must be measured, corresponding to: output drive low (IOL), output drive high (IOH), input leakage low (IIL), input leakage high (IIH), maximum input voltage for a logic 0 (VIL) and minimum input voltage for logic 1 (VIH). Therefore the total time to measure/apply 6 voltages for an IC with P pins is:
6P(TMeasure+4P/fTCK)=6PTMeasure+24P2/fTCK 
For an IC with 100 signal pins, fTCK=10 MHz, and TMeasure=10 xcexcs, the test time would be approximately 27 ms, and the number of test vectors would be 270,000. For an IC with 1000 signal pins and FTCK=10 MHz, the test time would be approximately 2.7 seconds, and the number of test vectors would be 27,000,000. The test time for a conventional tester having parallel access to all signal pins of the IC, and having a parametric measurement unit per pin, is typically 20 ms, regardless of the number of pins, and the number of vectors would be typically fewer than a few thousand.
There is a need for a method and circuit architecture which reduces the circuit node access time via an analog bus from the prior art method that is proportional to the square of the number of pins on the IC.
The present invention seeks to provide a circuit node sequential access method, and an IEEE 1149.4 compatible circuit for use therewith, in which the time to access a plurality of nodes is linearly proportional to the number of nodes accessed.
The present invention provides a method in which, after the BSRs have been initialized in the manner explained earlier to access the first of a plurality of circuit nodes, the number of clock cycles required to access subsequent circuit nodes may be reduced by simply shifting the switch enabling bit from one BSR to the next while preventing the TAP controller from altering the shifted boundary module bit values during the Capture-DR state and altering the state of other analog switches and/or signal node drivers during the UpdateDR state. This may be achieved by suppressing the capture operation when the TAP controller is sequenced through the Capture-DR state.
The method of the present invention is generally defined as a method for sequentially accessing circuit nodes in an IEEE 1149.4 compatible mixed-signal circuit having a TAP controller, a boundary scan register having boundary modules associated with each circuit node, analog busses for accessing the circuit nodes and connecting analog pins and each boundary module, the boundary modules including an analog boundary module having analog switches for selectively accessing the busses, the boundary register including shift register elements and associated update latches for controlling the analog switches, the method comprising initializing the boundary modules with logic values including an analog switch enabling logic value for enabling a switch associated with the first of the circuit nodes and enabling the switch; monitoring or driving the first signal node via the analog busses; suppressing capture mode in each boundary module; and for each additional circuit node to be accessed, shifting the switch enabling logic value from the boundary module containing the logic value to the next boundary module associated with a next signal node to be accessed and enabling a switch associated therewith; and monitoring or driving the next signal node via the analog bus.
Circuitry, constructed according to the present invention, intercepts control signals between the TAP controller and the ABMs, such that when a register bit is set, the ABM register contents are not altered during the CaptureDR state. When the CaptureDR state is thus prevented from affecting the ABMs, it is possible to update ABM analog switch settings, then shift enabling bits in the scan register from one analog switch controlling register element in an ABM to another ABM, and then perform a second update without an intervening capture. In this way, analog signals at a plurality of analog pins can be accessed with only a few shift clock cycles between each access, without the need to re-initialize the ABMs between circuit node accesses.
According to another aspect of the present invention, there is provided an improvement in an IEEE 1149.4 compatible mixed-signal circuit having a plurality of circuit nodes, analog busses for accessing the signal nodes, a TAP controller having a plurality of states including ShiftDR, UpdateDR and CaptureDR, an analog boundary module associated with each the circuit node, each module having boundary scan cells, each scan cell having an update latch, analog switches for selectively accessing the busses and boundary scan cells for controlling the analog switches, the improvement comprising circuit means for configuring the circuit in a Rapid Access mode to facilitate rapid sequential access of the circuit nodes, the circuit means being the responsive to a Rapid Access enabling signal for suppressing capture in the boundary scan cells to permit serial shifting of logic values in the boundary scan register without altering shifted logic values or the state of other analog switches.